Senior Staff Engineer - Design Verification

Senior Staff Engineer- Design Verification

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You are a dynamic engineer with working experience in RTL implementation, verification, flow automation with TCL and understanding protocols. You should have a passion for working with the best of the brains in the industry in developing end-to-end solutions and deploying them at our premier customer base. Your technical excellence and analytical skills, coupled with strong communication and interpersonal skills, make you a valuable asset to any team. You excel in communication, teamwork, and multitasking, and have experience working in cross-functional, multi-site environments.

What You'll Be Doing:

• Working closely with a world-class R&D team, you'll be at the center of developing and bringing an end-to-end solution to our wide variety of customers in the domain of Silicon Lifecycle Management (SLM).
• Working closely with customers, you will bring the detailed requirements into the factory to enable R&D for a strong, robust, and successful product development.
• Working closely with product development team, you will validate and end-to-end solution both internally (before shipment) as well as in customer environment.
• Driving the deployment and smooth execution of SLM solutions into customers' projects.
• Enabling customers to realize the value of silicon health monitoring throughout the lifecycle of silicon bring-up, validation, through in-field operations.

The Impact You Will Have:

• Enhancing Synopsys' Silicon Lifecycle Management (SLM) IP portfolio and end-to-end solution especially in the growing field of multi-die domain.
• Driving the adoption of Synopsys' SLM solutions at premier customer base worldwide.
• Influencing the development of next-generation SLM IPs and solutions.

What You'll Need:

• BSEE/MSEE in Electrical Engineering, Computer Engineering, or related field.
• 6+ years of hands-on experience with RTL design and verification, with exposure to Design-for-Test (DFT).
• High level understanding of In-System-Testing.
• Knowledge of PCIe & USB High speed interface protocols.
• In-depth knowledge of AXI protocol and working experience.
• In-depth knowledge of APB protocol and working experience.
• Knowledge of AXI Fabric/NOC.
• Exposure of IP/SoC design of Data transfer, Handshaking signals, FIFOs, Memory Address Maps, DMA etc.
• Strong SoC, IP verification skills with Complex testbenches with Verilog, SV & UVM and with BFM, other modules.
• Preferred basic exposure to RTL/Spyglass/Lint/CDC and basic synthesis and STA.
• Basic understanding of JTAG TAP protocol.
• Basic understanding of SPI interface protocol.
• Basic understanding of SCAN.
• Ability to evaluate technical suggestions from customers and work with internal teams (product management/R&D) to make decisions
• Customer facing experience is a plus – educating/guiding customer on technical details of a solution
• Good to have: Hands-on bring-up and debug experience of silicon is a plus Architecture/micro-architecture experience

The Team You'll Be A Part Of:

As part of the Silicon Lifecycle Management (SLM) solutions team, you will collaborate with global R&D teams to develop world-class IPs and end-to-end solutions to address silicon health issues at premier data center, AI, and automotive customers. Our team is dedicated to bringing solutions to enhance the life of a silicon anywhere it belongs.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.