DFM Engineer

DFM Engineer

Samsung is a world leader in advanced semiconductor technology, founded on the belief that the pursuit of excellence creates a better world. At Samsung Austin Semiconductor (SAS), we are Innovating Today to Power the Devices of Tomorrow.

Position Summary

We are seeking a skilled and motivated DFM engineer to join the team. The Samsung Austin Design For Manufacturing (DFM) team is part of the Yield department and is focused on incoming technology transfer, product optimization, new product introductions, yield improvement, process margin improvement, and performance enhancement. As part of the Advanced Node Technology Development team, you will provide data solutions in a high volume production environment as well as optimization of newer products and technologies. The ideal candidate will have experience in semiconductor layout and design, Cadence software, PDK development, and design rule development. Proficiency in Python or similar scripting languages is essential for automation and workflow enhancements. The role is critical in ensuring our designs are optimized for the semiconductor manufacturing process.

Role and Responsibilities

• Collaborate with layout and process integration engineering teams to develop and implement DFM guidelines and checks.
• Drive DFM methodologies throughout the physical design flow, focusing on manufacturability, yield, and reliability.
• Interface with other international counterparts to align and collaborate with their DFM group.
• Perform critical area analysis (CAA), OPC simulation, SVRF/TVF, and CMP modeling.
• Develop and maintain automation scripts (Python, bash-shell, tlc, etc) to support DFM dataprep and analysis.
• Troubleshoot and resolve DRC, ORC, and other DRM violations and coordinate with process integration or other layout teams.
• Communicate technical information to senior leadership within and outside of the department through presentations.
• Complete assigned duties in a timely manner.

Skills and Qualifications

Minimum Qualifications:

• B.S, M.S, or PhD in Electrical Engineering, Computer Engineering, or related field.
• 3-8 years of relevant industry experience in DFM, physical design, or layout.
• Experience with the semiconductor industry and how layout is affected by the process - layout dependent effects.
• Hands-on experience with Calibre and foundry DFM decks.
• Strong scripting skills in Python, or Shell for flow automation.
• Experience in PDK development or validation, preferred with advanced nodes of 14nm or lower.

Preferred Qualifications:

• Familiarity with GDS/OASIS data formats and layout tools (ex: Cadence Virtuoso).
• Understands basics of semiconductor device & fabrication through coursework and/or work experience.
• Strong analytical and debugging skills.
• Excellent communication and cross-functional collaboration skills.
• Experience building Machine learning models is a plus.
• Strong core values including: Integrity, Respect, Teamwork, Quality, and Continuous Learning.
• Proven skills of peer leadership, and mentoring of junior level engineers.
• Demonstrate ability to meet deadlines and commitments.
• Have the ability to work on different shifts based on project need.

The current base salary range for this role is between $70,480- $252,420. Individual base pay rates will depend on factors including education, skills, qualifications, and experience. Total compensation for this position will include a competitive benefits package and may include participation in company incentive compensation programs, which are based on factors including organizational and individual performance.

We offer a comprehensive benefits package, including:

• Medical, dental, and vision insurance
• Life insurance and 401(k) matching with immediate vesting
• Onsite café(s) and workout facilities
• Paid maternity and paternity leave
• Paid time off (PTO) + 2 personal holidays and 10 regular holidays
• Wellness incentives and MORE

Eligible full-time employees (salaried or hourly) may also receive MBO bonuses based on company, division, and individual performance.

All positions at SAS are full-time on-site.

This role requires access to information subject to U.S. export control laws. Applicants must be authorized to access such information or eligible for government authorization.

By submitting an application, you agree not to disclose to Samsung—or encourage Samsung to use—any confidential or proprietary information (including trade secrets) belonging to a current or former employer or other entity.