SMTS Verification Engineering

Smts Verification Engineer

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional SMTS Verification Engineer to join our Security team in Bangalore, India. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer.

As a SMTS Verification Engineer, you'll play a pivotal role in the verification of secure ASIC cores developed by Rambus Security Division (RSD), working with cross functional teams including ASIC design engineers and architects, other verification engineers and system test engineers, security experts, and cryptographers. Cryptography and hardware security experience is not required, but an ability to, and interest in, learning about these areas is important. In this full-time role, you'll report directly to our Director Verification Engineering.

Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work.

Responsibilities

Design and implement verification test plans, testbenches, infrastructure, and platforms to produce thoroughly verified and robust products

Implement best verification practices and improve on the existing methodologies and flows

Tackle sophisticated problems and develop scalable solutions that work across platforms

Assist with all existing and future roadmap hardware project phases – bring-up, testing, debug and coverage analysis

Work with release team to support customer integration and other requests.

Qualifications

BS or MS degree in electrical or computer engineering or closely related degree strongly preferred; but substantial, relevant, outstanding work experience may substitute in some cases

Four or more years of experience working as a verification engineer or related field

Strong written and verbal communication skills: ability to explain complex concepts in front of technical audience

Exposure to block-level and/or system-level verification

Good technical competence that includes a track record of effective verification of complex and configurable digital designs

Good understanding of standard ASIC verification techniques, including:

Test planning

Testbench creation

Code and functional coverage

Directed and SystemVerilog-based constrained random stimulus generation

Self-checking – scoreboards, predictors, or reference models

Assertions

Solid understanding of verification methodologies (UVM or OVM) and standard testbench languages

Comfortable with Unix development environments (make, scripting, SVN, etc.)

Ability to support lint/lec checking and automation using perl or python scripting

Regression and coverage management for existing and planned product families.

Experience with bug tracking, issue tracking and agile project management.

Familiarity with advanced verification techniques such as object-oriented testbenches and/or formal verification

Beneficial Experience:

Experience developing object-oriented testbench infrastructure in C/C++, OVM, or UVM

Familiarity with IP integration, IP core delivery, and handoff issues

Data, software, and/or network security; cryptography

Ability to work with technical writers in the production of technical documentation

Personal Attributes:

Excellent written, verbal, and interpersonal communication skills

Able to communicate ideas in both technical and user-friendly language

Able and willing to work in a team-oriented, collaborative environment

Able to coordinate with internal and external teams across time zones

A demonstrated ability to prioritize and execute tasks so as to achieve goals in an innovative, fast-paced, and often high-pressure environment

Proven analytical and creative problem-solving abilities

Passion for writing clean and neat code that adheres to coding standards