STA Engineer

STA Engineer

Quest Global delivers world-class end-to-end engineering solutions by leveraging our deep industry knowledge and digital expertise. By bringing together technologies and industries, alongside the contributions of diverse individuals and their areas of expertise, we are able to solve problems better, faster. This multi-dimensional approach enables us to solve the most critical and large-scale challenges across the aerospace & defense, automotive, energy, hi-tech, healthcare, medical devices, rail and semiconductor industries.

We are looking for humble geniuses, who believe that engineering has the potential to make the impossible possible; innovators, who are not only inspired by technology and innovation, but also perpetually driven to design, develop, and test as a trusted partner for Fortune 500 customers. As a team of remarkably diverse engineers, we recognize that what we are really engineering is a brighter future for us all. If you want to contribute to meaningful work and be part of an organization that truly believes when you win, we all win, and when you fail, we all learn, then we're eager to hear from you. The achievers and courageous challenge-crushers we seek, have the following characteristics and skills.

What You Will Do:

• Develop and validate timing constraints for intricate SoC designs.
• Expertise in Synthesis, Equivalency Checking and STA
• Must have Block Level and Multi-voltage Timing Closure experience. Top Level Timing Closure experience a plus.
• Experience with Synopsys Tools – Synopsys DC/FC for Synthesis, Synopsys Formality for Equivalency Checking and Synopsys PrimeTime for STA
• Define and implement timing signoff methodologies, including process corners, derates, and uncertainties.
• Conduct pre-route timing checks and quality of results (QoR) analysis.
• Automate timing analysis processes using scripting languages such as Tcl or Perl.
• Provide guidance on clock tree synthesis and optimization for energy-efficient designs.
• Ensure compliance with timing signoff checklists and criteria.

What You Will Bring:

• Experience with high-complexity silicon in advanced technology nodes.
• Familiarity with timing constraint development for hierarchical designs.
• Knowledge of clock tree planning and implementation for SoCs.
• Experience with timing ECO creation and final timing signoff.
• Proficiency in using STA tools (e.g., PrimeTime, TCM, Tempus) and scripting languages (e.g., Tcl, Perl).
• Proficiency in using synthesis tools (Genus)
• Strong understanding of ASIC design flows, including RTL and place-and-route.
• Excellent problem-solving skills and attention to detail.
• Effective communication and teamwork abilities.
• Bachelors and 8+ years of related experience; at this level post-graduate coursework may be desirable or Masters degree and 6+ years of related experience or PhD and 3+ years of related experience.

Pay Range: $120,000K - $190,000K

This role is considered an on-site position located in Palo Alto, California. You must be able to commute to and from the location with your own transportation arrangements to meet the required working hours.