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Senior Engineer DV

Develop and execute constrained random verification environments for ARM-based SoC chips
Bangalore
Senior
yesterday
Quest Global

Quest Global

A global engineering services company that provides solutions across various industries including aerospace, automotive, energy, and healthcare.

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Job Title

Job Requirements:

Job Responsibility:

Knowledge of code coverage using features in existing simulators or stand-alone tools like Surecov, HDL score etc.

Working on full chip verification and OVM/UVM Methodology, System Verilog is a must with 3+ years of recent work experience, worked on passing test cases, test benches, building environment.

Knowledge of functional coverage using HVL language features or assertions a plus.

Should be ARM based SoC verification only. No need to mention tools.

Proficiency in one scripting language like Perl, C++, Python, Unix Make, Unix Shell Scripts etc.

Desired Skills & Experience:

Experience level 3 to 5 years.

Strong domain knowledge on one or more - PCIe, USB, Ethernet, ARM, AHB/AXI, AMBA, Networking, CPU, ARM, Graphics (DDR, PCIE, USB).

Should have worked on SOC verification on at least one project with constrained random methodology (OVM/UVM).

Good in concepts Code coverage and functional coverage.

Expertise in Verilog and/or VHDL is desired.

Strong in SV & OOPS

IP or SoC verification

Functional + code coverage

ARM based SoC verification

Capable of developing C tests

Working knowledge – SV/METH

Code coverage

Education:

B.Tech/B.E., in Electronics/Telecommunication, Electrical OR PG - M.Tech/M.E, in (Electrical, Electronics/Telecommunication)

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Senior Engineer DV
Bangalore
Engineering
About Quest Global
A global engineering services company that provides solutions across various industries including aerospace, automotive, energy, and healthcare.