Test Plan Writing, Knowledgeable in UVM and System Verilog, Debugging RTL issues, Coverage Writing and SVA Waveform Debug Using Verdi. Must Be Proficient in IP Verification/SOC Verification. The Ideal Candidate For The Senior Design Verification Engineer Position Will Have A Strong Background in ASIC/FPGA Verification Methodologies, Experience With Formal Verification Tools, And A Proven Track Record of Delivering High-Quality Verification Results. In Addition, The Candidate Should Possess Excellent Communication Skills, The Ability to Work Effectively in a Team Environment, And A Passion For Solving Complex Technical Challenges.