Mixed - signal IC Design & Verification Engineer

Job Title

Support the development of customers custom analog compute-in-memory (CIM) dies, embedding high-precision, low-leakage charge-domain MACs within a DRAM-inspired array for ultra-efficient AI inference. This role involves analog circuit design, mixed-signal co-simulation, interface verification, and close coordination with RTL and layout teams to ensure manufacturable, high-yield silicon.

Responsibilities:

• Design analog front-end circuits, ADCs/DACs, comparators, and charge-domain memory circuits supporting 4–8b MACs per cell.
• Model and simulate analog/mixed-signal circuits for noise, reliability, mismatch, and variation-aware robustness under workload stress.
• Develop and verify mixed-signal interfaces between analog compute arrays and digital controllers, including timing and calibration logic.
• Implement fault correction schemes such as ECC, BIST, and redundancy logic for multi-bit precision memory-CIM arrays.
• Integrate analog circuits into digital layout flow, ensuring compatibility across multiple voltage and clock domains.
• Collaborate with digital design teams on interface definitions and with layout teams for floorplan, power grid, and isolation strategies.
• Contribute to tapeout execution: DRC/LVS signoff, corner simulation, test mode planning, and silicon debug hooks.

Work Experience:

• 8+ years of production-level analog/mixed-signal IC design, including experience in embedded memory, compute-in-memory, or high-precision sensor front ends.
• Deep expertise in ADC/DAC design (SAR, pipelined, current-steering) and analog compute blocks (capacitive MACs, charge integrators).
• Strong understanding of multi-voltage and multi-clock domain integration, including domain isolation, level shifting, and interface timing closure.
• Demonstrated experience in analog/digital co-design with mixed-signal floorplanning and layout coordination.
• Familiarity with ECC, redundancy logic, and self-test/BIST for analog memory arrays.
• Tools: Cadence Virtuoso, Spectre, Verilog-AMS, Synopsys CustomSim, Calibre, mixed-signal simulation environments.
• Experience with advanced process nodes including 22nm/18nm FDSOI and 12nm FinFET is a strong plus.