Job Title

Hands-on experience with SRAM layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc

Should have worked on at least 7nm Finfet process technologies. 6nm, 5nm, 4nm,3nm will be an added advantage.

Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning physicals across the Memory

Good hold on IR/EM related issues in memory layouts.

Experience Required: 3+ yrs

Must have worked on cadence tools for layout design and Cadence/Mentor tools for physical verification checks.

Strong knowledge of ultra-deep sub-micron layout design related challenges and good understanding of DFM guidelines.

Experience or strong interest in memory Macros or Memory Compiler

Excellent and demonstrated team player with ability to work with external customers.

Memory Layout Engineer