Own end-to-end Physical Design flow: floorplan → placement → CTS → routing → signoff
Lead and guide PD engineers on daily tasks and priorities
Ensure timing, power, area, IR/EM, and DRC/LVS closure
Work closely with RTL, STA, DFT, and Top/Chip teams
Track progress, risks, and blockers; report status to PD manager / program manager
Support ECOs, late changes, and tape-out readiness
Ensure delivery meets customer and project milestones
Strong hands-on experience with Cadence Innovus / Synopsys ICC2
Solid understanding of PnR, CTS, STA, IR/EM, PV
Experience across advanced nodes (e.g., 3nm–28nm) is a plus
Scripting knowledge (TCL/Shell) for flow automation