DFT Engineer

DFT Engineer

Quest Global delivers world-class end-to-end engineering solutions by leveraging our deep industry knowledge and digital expertise. By bringing together technologies and industries, alongside the contributions of diverse individuals and their areas of expertise, we are able to solve problems better, faster. This multi-dimensional approach enables us to solve the most critical and large-scale challenges across the aerospace & defense, automotive, energy, hi-tech, healthcare, medical devices, rail and semiconductor industries.

We are looking for humble geniuses, who believe that engineering has the potential to make the impossible possible; innovators, who are not only inspired by technology and innovation, but also perpetually driven to design, develop, and test as a trusted partner for Fortune 500 customers. As a team of remarkably diverse engineers, we recognize that what we are really engineering is a brighter future for us all. If you want to contribute to meaningful work and be part of an organization that truly believes when you win, we all win, and when you fail, we all learn, then we're eager to hear from you. The achievers and courageous challenge-crushers we seek, have the following characteristics and skills

What You Will Do:

• Strong theoretical and conceptual knowledge of DFT principles, including Scan, Logic Built-In Self-Test (LBIST), and Memory Built-In Self-Test (MBIST) algorithms.
• Proven experience in gate-level simulation and Design Verification (DV) of DFT structures.
• Specific expertise in gate-level simulation of MBIST (Memory BIST).
• Specific experience with MBIST verification using PG (Power-Ground) netlists is highly desired.

What You Will Bring:

• Experience as a DFT architect for chip and block level IPs.
• Direct experience with MBIST verification for memory retention test is a core requirement.
• Hands-on experience with DFT implementation/insertion at the block level is required.
• Strong Siemens EDA/Mentor Graphics Tessent experience. The core requirement is experience with the full flow, including gate-level work, rather than just high-level RTL verification.
• Experience with MPR simulation in gate level or block level DFT insertion very important

Educational Qualification: MS or PHD in Electrical Engineering with 10+ Years of Experience

Pay Range: $120,000K - $190,000K

Work Requirements:

• This role is considered an on-site position located in Palo Alto, California
• You must be able to commute to and from the location with your own transportation arrangements to meet the required working hours.