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Design Verification Engineer
Design and implement verification environments for large System-on-Chip designs
Bangalore
Senior
3 weeks ago
Qualitest
A global provider of AI-powered quality engineering, software testing, and quality assurance services.
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Design Verification Engineer
The main requirement is top notch Verification engineers, and less relevant the specific experience. We can consider a range of years of experience (above 4 years), and again, the main requirement is excellence. Top talent Chip Verification engineers, with range of experience above 4 years: 4-7, 7-10, 10+ years. Experience in full Chip verification cycle: test planning, verification code writing, tests and RTL debug, verification closure. Experience writing in SystemVerilog/UVM or Specman/E. Preferred: Experience in "Full Chip" verification of large SoC chips. Creating and using verification components and environments in standard verification methodology. Debugging tests with design engineers to deliver functionally correct design blocks.
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