Senior DFT Engineer

Senior Dft Design Engineer

Are you passionate about computer graphics and disrupting the industry with your innovation and working with leading engineers on Intel's latest GPU/CPU architecture? Do you love collaborating with diverse teams to help achieve Best-In-Class visual experiences that enable users to immerse themselves in a new visual future? Then AI SOC Engineering team has opportunities for you. Our Hardware development team designs and validates the future of GPU Cores. We are looking for a Senior DFT Design Engineer to join our team who are ready to make significant impacts in graphics and visual computing.

As a member of the AI SOC Engineering group, you will be responsible for one or more of the following activities:

• Work on the design, RTL/GLS validation, automation, and/or timing analysis for Scan/ATPG and/or DFT/JTAG controller
• Contribute or be involved with trace/pattern generation efforts as well as post-silicon enabling, debug support, and/or analysis of the DFx features/content types you are responsible for.
• Develop the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs.
• Participate in the definition of architecture and microarchitecture features of the block being designed.
• Apply various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
• Review the verification plan and implementation to ensure design features are verified correctly across verification hierarchies, drives unit level verification, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
• Support SoC customers to ensure high-quality integration of the GPU block.

The ideal candidate will exhibit the following traits/skills:

• Excellent written and verbal communication skills
• Demonstrate leadership ability in driving execution
• Demonstrate teamwork, problem solving and influencing skills
• Ability to work with different geographical locations

Qualifications:

Minimum Qualifications:

Bachelors Degree in Electrical Engineering, Computer Engineering, or related STEM degree and 5+ years of industry experience OR Masters in Electrical Engineering, Computer Engineering or related STEM degree and 3+ years of industry experience OR PhD in Electrical Engineering, Computer Engineering or related STEM degree and 2+ years of industry experience

Your experience should be in the following:

• At least one of the key DFT features such as TAP/JTAG, Scan/ATPG or Array DFT (MBIST/PBIST)
• SoC or IP DFT design, integration or verification
• EDA tools such as ATPG tools, Siemens Tessent shell, VCS simulation and/or debug tools.

Preferred Qualifications:

• Silicon enabling debug or test pattern development experience
• Design automation skills and proficiency in programming or scripting languages
• Structural design flows, including timing, routing, placement or clocking analysis
• High volume manufacturing requirements and test flows
• 3D, media and display graphics pipelines
• SoC architecture

Job Type: Experienced Hire

Shift: Shift 1 (United States of America)

Primary Location: US, California, Folsom

Additional Locations: US, Arizona, Phoenix, US, California, Santa Clara, US, Oregon, Hillsboro

Business Group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them.

Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits: We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as benefit programs which include health, retirement, and vacation. Find more information about all of our amazing benefits here.

Annual Salary Range for jobs which could be performed in the US: $161,230.00-227,620.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role: This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. Job posting details (such as work model, location, or time type) are subject to change.