Principal CMP Process Engineer

Process Engineer

We are looking for a Process Engineer role in preparation for the formation of the joint venture of NXP and VIS, known as VSMC.

This posting is for a CMP and/or Wafer Bond Process Engineer in a high volume, 300mm wafer manufacturing environment. The qualified candidate must possess process knowledge of CMP/wafer grind and experience with the MIRRA and IPEC polishers &/or Disco grinder equipment sets. They must be competent problem solvers, capable of applying logic to isolate and determine root cause. They must be self-motivated, tactical, and able to work with minimal direction. The candidate must have the ability to make good decisions with limited time and data in a quickly changing environment. The candidate will be expected to deal with multiple issues and shifting priorities, and as such, must be able to interact professionally with management, manufacturing and maintenance to improve overall area performance. The candidate must have strong verbal and written communication skills.

Primary Responsibilities

• Sustain and improve CMP/Wafer Bond processes to meet manufacturing demand for throughput and cycle time
• Improve quality levels by driving to root cause to eliminate scrap and yield loss mechanisms
• Identify and execute cost reduction solutions to meet Factory budget goals
• Collaborate with integration, device, Manufacturing, Maintenance, and Process teams to improve overall CMP and Bond process performance
• Participate in and/or lead cross-functional and lean activity teams
• Reduce defectivity mechanisms and improve process control
• Work with minimal supervision, balancing competing priorities, to serve the needs of the engineering and manufacturing communities
• Drive equipment performance to maximize capacity and yield performance
• Improve cost performance of equipment

• Mentor engineers and provide technical leadership in CMP process improvement

Required Skills/Experience

• B.S. Degree in Electrical Engineering, Materials Science, Solid State Physics or other relevant engineering discipline is required.
• Minimum 15 years semiconductor CMP process engineering experience is required.
• Process knowledge of CMP/wafer grind and experience with the MIRRA and IPEC polishers &/or Disco grinder equipment sets.
• Strong background in SPC & FDC is required.
• Positive interpersonal skills, highly energetic and self-motivated.
• Outstanding written and verbal communication skills.
• Ability to manage and execute multiple projects simultaneously and shift priorities to meet business needs.
• Demonstrated application of structured problem solving methodology along with creative thinking to drive to failure root cause.
• Demonstrated ability to meet commitments and deliver results.
• Demonstrated experience with Design of Experiments.
• Demonstrated experience with automated fault detection and control systems.
• General understanding of equipment component behavior.