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Design-for-test engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.
What you'll be doing:
As a member in our team, you will be responsible for the design and implementation of state-of-the-art designs in test access mechanisms, memory BIST and scan compression.
You'll be responsible for DFT verification environment setup, own DFT verification and bringup tasks for Clocks, Boundary Scan, Analog and MBIST, Scan, etc. You'll have chance to take the lead role for DFT verifications and bringup.
In long term, you can be a DFT lead for verification or extend the expertise to DFT design or implementation.
What we need to see:
MS EE or PhD in DFT
Good understanding on ASIC design and verification
Hands on experience on at least one DFT feature: Boundary Scan, 1500, MBIST, Scan, ATPG
Experience in silicon debug and bring-up on the ATE is a plus
Good exposure to clock design, timing/STA, place-n-route or power is a plus
Excellent analytical skills in verification and debug
Strong programming and scripting skills in Perl, Python or Tcl desired
Excellent written and oral communication skills in English with the curiosity to work on challenges
NVIDIA is widely considered to be one of the technology world's most desirable employers. We have some of the most brilliant and talented people on the planet working for us. If you're creative and autonomous, we want to hear from you!