Custom SOC IP Verification Engineer

Senior Custom SOC/IP Verification Engineer

IDIA is seeking a Senior Custom SOC/IP Verification Engineer to verify the next generation SoC and IP solutions! We are looking for special individuals with desire to deliver innovative products. Together, we will build the next generation of life changing custom SOCs! If you are a motivated individual that understands how complex SOC and IPs are built, has intimate knowledge of client requirements, and understand various development cycles, this is your place to be.

This role demands an expert in ASIC verification methodologies and infrastructure development, coupled with extensive knowledge of key industry protocols such as AMBA (AXI, CHI, ACE, ATB) and PCIe. We are specifically seeking a skilled ASIC Verification Engineer with deep knowledge of System Verilog, UVM, and C++, along with a solid grasp of ASIC verification methodologies. You will be instrumental in defining and implementing cutting-edge verification strategies, building robust test environments, and ensuring the functional correctness of complex high-performance SOCs and their constituent IPs.

What You'll Be Doing

• Responsible for ASIC design verification for various processing blocks within a SOC.
• Work on key aspects of verification planning and execution, including the development of innovative methodologies.
• Design and implement constrained-random and directed testbenches using System Verilog and UVM to achieve verification closure.
• Develop and analyze coverage metrics to ensure comprehensive verification.
• Collaborate extensively with Architecture, SW/FW, Design, Modeling, Emulation, and Post-Silicon Validation teams to ensure flawless verification plans and execution.

What We Need To See

• B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or a related field (or equivalent experience).
• 7+ years of experience in ASIC verification with a proven track record of first-pass success.
• Strong knowledge of System Verilog and UVM methodology.
• Experience running and delivering complex mixed language UVM and C++ testbenches.
• Hands-on experience developing tools and infrastructure using Perl or Python.
• Proficiency in scripting languages (Python, Perl, TCL) and working knowledge of C/C++ for testbench or model integration.
• Deep understanding of AMBA protocols, especially AXI, ACE, and CHI or equivalent experience.
• Experience with complex subsystems like ARM CPU complex, LPDDR, HBM, GPUs, DLA, PCIe, or Network on chip.
• A clear understanding of complexities involved with various design verification tools and performance verification.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until August 14, 2025. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.