Sr/principal Engineer, FE CPIE RAM Quality And OPNS Engineering

Micron Technology Job Opportunity

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Responsibilities and Tasks:

• Establish strategy, models and systems to improve wafer at risk reduction for RAM Defense line hardening.

• Establish strategy, model and systems to improve RAM quality control and reduce defect OOC% variation.

• Establish strategy, model and systems to improve RAM operation efficiency to achieve labor productivity improvement, Cycle time performance, tool utilization performance for lower cost.

• Establish and improve BKM (Best Known Method) related to RAM defense line hardening and operation efficiency.

• Ensure BKM sharing spans across all sites regardless of technology and/or site mission differences.

• Implement abnormal analysis and improvement.

• Lead Copy Smart Team (CST), facilitate taskforce discussion and drive RAM network alignment on strategy business process and roadmap to achieve area objectives and deliver to timelines/commitments.

• Support and performs audit and establish metrics that can efficiently audit adoption rate and compliance to business process, BKM and strategy.

• Actively provide recommendations to improve and optimize programs and processes to the respective program and/or process owners.

• Manage projects with proper Project Management process with metric to track project success.

• Track Fab performance metrics for benchmarking purposes. Identify gaps and area of improvements for Fabs.

• Provide tactical support and coordination for the Fabs as required for issues of People, Safety, Time to Mature cummulative Yield, Quality, Cost, and Cycle Time.

• Communicate clearly and present strategy and updates to network members and leaders.

Requirements:

• Masters/Bachelors in Engineering

• Relevant working experiences in RDA and/or Metrology

• Willing and capable of international travel, including Extended International Business Travel (EIBT) assignment to 6 months as needed, to accomplish the goals.

• Good communication skill, maintain a strong and open relationship with peer group and appropriate team members in other functional areas such as Process Integration Engineering, Quality Systems, Production Operations Management

• Promote worldwide sharing and transfer of area-specific domain knowledge

• Proficiency, experience and knowledge relating to product and test wafer capacity modeling, wafer at risk modeling, Failure Mode Effect Analysis (FMEA) concept and system, defect analysis tools, sampling strategy and systems, Statistical Process Control (SPC) tools, Cycle Time Management, tableau creation, SQL and Programming language and Organization Change Management have advantage.

Working Location: 1, North Coast Drive, Singapore 75743