MTS Process Integration Engineer, APTD

Process Integration Engineer For Advanced Packaging

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

The Advanced Packaging Technology Development (APTD) department at Micron Technology is at the forefront of innovation, driving the advancement of memory and storage Interconnects and Packaging solutions that transform how the world uses information. Micron is dedicated to developing innovative processes and technologies that enable the creation of next-generation semiconductor products which drive the AI revolution. By collaborating closely with our global R&D, equipment and materials suppliers, and manufacturing teams, we ensure the efficient development, transfer and implementation of new technology nodes, maintaining Micron's leadership in the industry.

As a Process Integration Engineer for Advanced Packaging, you will own the end-to-end integration of next generation package architectures like 2.5D, 3D stacking, HBM memory integration, and hybrid bonding. You'll lead new technology development and technology transfer, design DOEs, and analyze yield and reliability. You will coordinate across device, design, process, equipment, test, and manufacturing teams to deliver high performance multi-die technology.

Responsibilities:

Own package-level process integration across 2.5D/3D flows (wafer-to-wafer, chip-to-wafer, advanced interconnects), defining specs and process windows that meet high performance targets for HPC/AI products.

Develop and integrate semiconductor manufacturing processes; Design, optimize, and implement fabrication flows that seamlessly integrate multiple steps (lithography, etch, deposition, diffusion, CMP, and thin films) into cohesive production processes.

Plan, run, and analyze targeted experiments to validate new materials, process parameters, and design rules to improve yield and device performance. Design and execute DOEs on bonding, underfill, molding, stacking, and integration steps; Apply SPC to parametrics and yield detractors and close the loop with corrective actions.

Analyze yield, performance, and defect data. Utilize big data, physical, electrical, and defect data to root-cause process weaknesses, yield issues, and tool variances. Employ SPC and advanced analytics.

Lead technology transfer from TD to TD and HVM. Establish mask rules, materials, tool readiness, baseline qualification, and technology validation plans.

Hybrid bonding (CuCu + dielectric) integration; Set surface prep, planarity and alignment requirements, qualify W2W/C2W flows, and track defectivity and reliability.

Thermocompression & microbump flows; Optimize underfill, TC bonding windows, and pillar/bump geometries for high I/O assemblies.

HBM and interposer systems; Co-optimize TSV/interconnect routing and thermal paths to meet bandwidth/latency targets. Align package floorplans with chiplet partitioning.

Warpage engineering; Predict and mitigate wafer/die warpage via modeling, cure shrinkage controls, and material/process levers. Validate with inline metrology.

Metrology and inspection; Deploy SAM, IR microscopy, and emerging XRD warpage mapping to correlate process, defects, and reliability.

Minimum Qualifications:

MS or PhD in Materials Science, Chemical Engineering, or related field

10+ years experience in advanced packaging technology development (2.5D/3D, HBM)

Hands-on knowledge of advanced interconnects/TSV, die stacking, underfill, molding, and bonding flows

Proficiency in DOE/SPC and data analysis (e.g., JMP/Minitab/Python); demonstrated root-cause problem solving and yield improvement.

Experience with metrology: SAM, Xray/CT, IR, warpage profilers (shadow moiré/DIC)

Strong communication skills; ability to lead cross-functional teams and drive actions to closure in fast-paced environments.

Direct experience with hybrid bonding integration and reliability (W2W/C2W)

Demonstrated success in HBM and logic integration (including thermal co-optimization)

Warpage modeling and inline correlation experience

Deep familiarity with underfills, reworkable strategies, and TC bonding optimization

Candidates must have experience and the ability to adhere to cleanroom environment/EHS protocols. This role entails occasional travel to sites in Asia for integration development and transfer support.