Senior Staff DFT Engineer

DFT (Design for Test) Senior Staff Engineer

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Marvell's DCE (Data Cloud Engineering) is a global design team at the forefront of developing cutting-edge silicon products that power the most advanced applications and technologies in the semiconductor industry. We are excited to offer an excellent opportunity to join our Israel-based Switch SoC department as a DFT (Design for Test) Senior Staff Engineer. Our global Switch DFT group is responsible for the architecture, design implementation, validation, and execution of end-to-end testability strategies and DFT solutions for current and next-generation products that drive the future of data communication in a hyper-connected world of Cloud and AI.

What You Can Expect

• Be a part of highly experienced DFT team developing best-in-class high complexity products
• Execute on DFT tasks in multi-project environment
• Develop and improve DFT tools methodologies focusing on quality, customer needs and continuous improvements of the team processes.
• Complete DFT project activities, own implementation and validation of the DFT logic and providing patterns to the Product Engineering team
• Own the DFT sign-off to ensure bug-free design and high ATPG / MBIST coverage for the product
• Work with the post-silicon teams on debug support and to help root-cause any failures

What We're Looking For

• B.E/B.Tech or M.E/MTech Electrical engineering with 8+ years of experience in DFT
• Excellent design and debug skills for RTL/GL based simulations and ability to debug issues on Si.
• Proven hands-on experience and deep understanding of MBIST, Scan Insertion and ATPG including Pre-Si design stages and Post-Si bring up and products qualification support.
• Solid knowledge of standard DFT EDA tools (Mentor, SNPS) for Memory BIST, ATPG and Boundary Scan. Strong advantage if familiar with Tessent/Mentor DFT tools and methodologies
• Solid understanding of JTAG standards and their usage for DFT.
• Understanding and experience with timing closure and PD related aspects of VLSI flow and DFT Sign Off
• Proven problem-solving skills focusing on uncompromised quality, innovation and continuous learning and improvement.
• Strong communication, collaboration and teamwork skills and ability to work in global team environment

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We're dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us.