Principal Engineer, STA

Marvell Principal Full Chip STA Engineer

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

As member of the Physical Design team at Marvell you will have the opportunity to work on digital design for ASICs, Physical Implementation, Power Supply integrity checks Low Power design & Signoff. Opportunity to work for complete SoC design cycle of ASICs, starting from Architecture definition, feasibility planning/benchmarking for Power/Performance/Area/Yield to end-to-end design/Implementation/Signoff. Opportunity to work on challenging design architecture across Networking, Processor, Computing, automotive, Connectivity and Security, in the technology nodes across 3nm/5nm/7nm and more.

What You Can Expect

• As a Principal full chip STA engineer, you will be responsible for running/supporting/maintaining the Global Timing Flow using industry standard EDA tools for designing the next generation Multi-Ghz high-performance processor SOC chips in leading-edge CMOS process technology.
• Experienced in IP constraint development and integration, constraint management and pushdown, ECO flows is a must.
• Work with design teams across various disciplines such as Digital/RTL/Analog/DFT in helping them take their blocks (custom, PnR) through the global timing flow and making sure all the blocks meet timing requirements.
• Provide technical direction, coaching, and mentoring to employees on your team and others when necessary to achieve successful project outcomes.
• Writing scripts in TCL and Perl to achieve productivity enhancements through automation.

What We're Looking For

• BSEE or MS with 12+ years of experience running an industry standard EDA tool for global timing is required (PrimeTime preferred).
• Experience in tape-outs of high performance SOC is highly desired.
• Understanding of several timing-related concepts is required: setup, hold, clocking, timing corners, timing constraints, noise, and process variation.
• Knowledge of scripting languages such as Perl/TCL is required.
• Diligent, detail-oriented, and handle assignments with minimal supervision.
• Must possess good communication skills, self-driven individual and a good team player.
• #LI-MN1

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We're dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.