Analog Engineer Intern - Phd

Optical Digital Signal Processing (ODSP) Group Design Engineer

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Central Engineering works directly with the Optical Digital Signal Processing (ODSP) group to design physical layer ICs for high-speed fiber optic data communication, such as Transimpedance Amplifiers (TIAs), and drivers for Silicon Photonic (SiPho) and discrete Electro-absorption Modulators (EAMs) and Mach-Zehnder Interferometer Modulators (MZMs). This group is the market leader in delivering DSP transceivers that support 10Gbps to 1600Gbps systems. We address the bandwidth, capacity and power issues faced by cloud computing and mega data center networks. Our world class group leverages our core competencies in advanced circuit design to solve the world's ever-increasing desire to transmit more data for less power with fewer errors. We are continually first to market in Data Center, Metro and Long-Haul applications. As a member of the design group, the candidate will be responsible for design and validation of FET and BiCMOS circuits for high-speed broadband ICs that serve these applications.

What You Can Expect

• Understand the requirements of the product and how your block fits into it.
• Take ownership of a block to be delivered into one of Marvell's DSP transceivers.
• Evaluate tradeoffs between different circuit topologies
• Perform schematic capture and layout in Cadence, Virtuoso design environment.
• Run schematic level and post layout simulations to quantify and optimize circuit performance
• Document design and hold a design review with the design team.

What We're Looking For

Minimum Requirements:

• MS Degree in EE or related technical field(s)
• Strong fundamental circuit design knowledge
  • Detailed transistor level design
  • Device physics
  • Feedback and loop stability analysis
• Strong communication, presentation, and documentation skills.

• Design experience in either Cadence Virtuoso or Mentor Custom Compiler circuit design tools.
  • Experience with schematic capture, layout, and simulation.
• Knowledge of broadband design techniques.
• Knowledge of CMOS as well as SiGe Bipolar is a plus.
• Experience with a chip tape-out is a plus.