Location: New Taipei City, New Taipei
Company: Molex
Career Field: Engineering
Define specifications with the module architecture/system engineers.
Review, assess, provide feedback, and develop digital micro-architectures.
Generate RTL to comply with specifications, both manually and through automated generation.
Create a Cadence schematic database of digital blocks using Virtuoso.
Perform System Verilog verification simulations for the design by creating test benches at the block level.
Execute logic synthesis and generate the physical layout.
Create DFT hooks and generate test patterns.
Execute remaining back-end tools, including place & route, static timing analysis, and ATPG.
Proficiency in System Verilog/Verilog language and simulation.
Proficiency in scripting languages such as Python, TCL, UNIX/LINUX shell, PERL, C/C++.
Experience with synthesis and static timing analysis.
Experience with place & route using Cadence Virtuoso, and verifying database vs schematics.
Knowledge of System Verilog assertions and functional coverage.
Experience with formal verification.
Familiarity with scan testing and participation in design reviews.
Excellent analytical, problem-solving, and debugging skills.
Good communication and teamwork skills, with the ability to work effectively in cross-functional teams.
Knowledge of SerDes circuits/IP.
Knowledge of LCOS or LCD IC architecture, column driver, MIPI interface.
Good understanding mixed-signal design and EDA tool configuration/setup.
Knowledge of liquid crystal phase modulators.