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Static Timing Analysis Engineer, Full - chip STA

Lead full-chip STA timing signoff and optimize clock tree for power and performance
Mountain View, California, United States
Mid-Level
$138,000 – 198,000 USD / year
6 hours agoBe an early applicant
Google

Google

Operates a global search, advertising, cloud, and consumer technology ecosystem that organizes and monetizes access to digital information.

Static Timing Analysis Engineer

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $138,000-$198,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.

Responsibilities:

  • Deliver system-on-chip (SoC) Static Timing Analysis.
  • Define SoC timing signoff process corners, derates, uncertainties and their tradeoffs.
  • Drive clock tree Jitter and implementation for SoCs to achieve best energy, performance and area.
  • Execute full chip timing constraint validation and timing signoff checklist criteria, perform full chip Static Timing Analysis (STA) and timing Engineering Change Order (ECO) creation, and oversee final timing signoff for SoCs.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law.

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Static Timing Analysis Engineer, Full - chip STA
Mountain View, California, United States
$138,000 – 198,000 USD / year
Engineering
About Google
Operates a global search, advertising, cloud, and consumer technology ecosystem that organizes and monetizes access to digital information.