Senior Silicon DFT Engineer
Senior Silicon DFT Engineer
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work on SOC Design for Test (DFT) Architecture to implement and validate from the SOC level. You will work on SOC level ATPG and MBIST pattern generation to deliver and support post-silicon bring-up, including subsystem level pattern retargeting. The role requires working with the product engineering team on silicon bring-up and writing basic scripts to automate the DFT flow. Additionally, you will communicate and work with multi-disciplined and multi-site teams.
The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first-party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.
Responsibilities include:
- Perform SOC level Memory Testing and repair feature verification, ATPG pattern generation, retarget and ensure coverage goals are met.
- Develop and release the SOC DFT STA Constraint and validation along with RTL signoff checks.
- Work on gate level simulation both no-timing and timing.
- Integrate SOC DFT, Scan architecture, IJTAG network integration and verification.
- Integrate and verify PHYs and Mixed-Signal IP DFT along with BSCAN.