Design Verification Engineer

Design Verification Engineer

Location: Bangalore / Pune

Experience: 5+ Years

We are looking for a hands-on Design Verification Engineer with strong experience in IP/SoC Verification to join our growing team.

Key Responsibilities:

• Hands-on experience in IP / SoC Verification
• Experience across one or more complete project cycles, including tape-out
• Strong design & verification failure debugging
• Development of test plans, testcases, and verification strategies
• System Verilog & UVM testbench coding
• Assertion / checker development
• Functional coverage development and coverage closure
• Debugging simulation and regression failures

Technical Skills Required:

• Verilog, System Verilog UVM Methodology
• Functional Coverage Assertions (SVA)

Protocol Knowledge (one or more):

• PCIe, Ethernet, CXL
• USB, CAN, LIN, Flex Ray
• AXI, AHB, APB