SI Engineer - Technical Leader

Signal Integrity Technical Leader

Working directly with ASIC and system design teams to evaluate design tradeoffs and optimize design performance / risk / cost / manufacturability

Drive next generation Serdes IP characterization/system feasibility studies

Design and analysis of multi-gigabit serial links/parallel bus in system development

Modeling and analyzing power delivery networks

Performing physical measurements to collect data for design validation and simulation correlations

Driving methodology enhancements and automation improving performance and efficiency

Development simulation tools with EDA vendor(s) whenever needed for analysis

Mentor junior engineers and interns

We're seeking a Signal Integrity Technical Leader for design and analysis of high speed interfaces and power distribution network. The candidate will participate in the definition/design/application of current and next generation ASIC, package, printed circuit board (PCB), and system interconnect. The individual will be the key person to work closely with system architects, ASIC engineers, CAD engineers and other very talented and knowledgeable cross-functional engineers in creation of next generation high performance networking products.

Self-motivation, strong teamwork, strong communication skills and out of the box thinking with the strong desire to innovate are essential. Ability to define a project schedule and requirements, then deliver to that schedule. In depth understanding of electromagnetic theory is required. Hands on experience with system development focused on Serdes IP selection, package design and simulation, DDR5, PCIE etc. Working knowledge of system level power integrity and budgeting (DC, AC, transient analysis) Strong tools knowledge on 2D/3D tools (HFSS/ADS/Hspice/PowerSI/PowerDC, etc.) Strong lab skills and measurement experience required (VNA/TDR/Scope/BERT, etc.)

PhD/MSEE combined with 5+ years of related experience, or BSEE combined with 10+ yrs related experience.