Senior Analog/mixed - signal IC Design Engineer - Acacia

Acacia Mixed-signal Ic Design Engineer

Acacia designs intelligent transceivers using advanced signal processing and photonic integration for the 100G, 400G, and 1T bit speed fiber optic transmission market deployed in data center, metro, long-haul, and ultra-long haul telecommunication networks.

We are a mixed-signal IC design group that develops high speed (>25Gb/s), and high accuracy, analog designs for optical communications products. We optimize design that will integrate into the ASIC. Our team interacts with other Acacia groups including digital/DSP design, system design, package design, and module design.

You will architect, design, layout, measure, and productize ultra-deep sub-micron-based CMOS products.

You will lead efforts for a large block on a complex chip, mentor team members and track deliverables, participate in peer review of complex IC designs and provide solid design methodology from conception to production.

You will also collaborate with packaging and hardware design team to ensure signal and power integrity specifications are met.

You will develop high-speed AMS circuits and best-in-class products that push the boundaries of what is possible.

BSEE degree with 12+ years of experience or equivalent or an MS degree with 8+ years of experience, or equivalent or a PhD with 5+ years of experience, or equivalent.

Design, simulation, and measurement of high-speed ICs in at least 3 areas below:

High speed serial links utilizing serializers, deserializers, and data converters, voltage regulators, output drivers, phase locked loops, clock transmission/propagation, opamps, programmable gain amplifiers, and equalization.

Experience with electrical transceiver applications including backplane and cable communications.

Experience with FinFET technology.

High-frequency layout experience a plus: passive component design: inductors, transformers, transmission-lines, etc.

Floorplanning (power/ground, digital/analog signal routing, etc.) experience.

Custom transistor layout experience.

Experience designing for manufacturability.

Experience with ESD laboratory practices and methodology.

Experience with Cadence (virtuoso), Spectre/APS/SpectreX, Matlab, EMX.

Experience with mixed-signal simulations in AMS.

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