Location: Folsom, CA
Duration: 1+ year with possible extensions
Pay Rate: $115-$120/HR
Position Overview: Oversees definition, design, verification, and documentation for ASIC development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Evaluates all aspects of the process flow from high-level design to synthesis, place and route, and timing and power use. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. May also review vendor capability to support development. 10+ years of experience in SoC Arch.
Drive initialization, reset flow and design implications to other blocks
Drive different clock domain crossing, distribution and dependency
Drive power-domains, level-shifting, power-management requirement
Drive DFX requirement – including BSCAN, JTAG
Focus is on interior chip architecture
Emphasis on SoC-level logic design and integration across multiple components
Role involves design engineering, not heavy RTL coding
Candidate should be able to extract technical details and build high-level architectural models
Responsible for reset flow, clock domain crossing, and power domain management
Needs to guide and analyze full data-path performance across blocks
Must be able to pivot and adapt based on evolving capabilities or design constraints
Involves verification alignment and ensuring architectural integrity
Professional Development: Gain hands-on experience with cutting-edge industry standards.
Collaborative Environment: Work with a supportive team committed to high-quality outcomes.
Impactful Work: Ensure our products meet rigorous quality and regulatory standards.
Apply today to take the next step in your career!