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Sr Principal Design Engineer

Own the design and optimization of high-performance memory IP micro-architecture
San Jose, California, United States
Senior
$154,000 – 286,000 USD / year
2 days ago
Cadence

Cadence

Provides electronic design automation software and IP for designing, verifying, and optimizing complex semiconductor chips and systems.
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At Cadence, We Hire And Develop Leaders And Innovators Who Want To Make An Impact On The World Of Technology.

Specific duties include:

  • Be responsible for high-performance memory IP architecture design, owning the IC micro-architecture, timing budget, power analysis platform development.
  • Proficiency in logic design, simulation, synthesis, STA and testing
  • Proficiency in Verilog/SystemVerilog and its simulation environment
  • Good knowledge of IC design for high-speed and low power
  • At least five years' experience driving complex IC development projects, excellent communication skills and the uncanny ability to both lead and contribute in a cooperative team environment.

Position Requirements:

  • Essential Qualifications: Must have BS degree with 8+ years of applicable experience, MS degree with 6+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics.
  • Essential that the individual demonstrates strong communication, verbal and written.
  • Experience on the memory IP is desired
  • Requires good communication skills in English.

The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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Sr Principal Design Engineer
San Jose, California, United States
$154,000 – 286,000 USD / year
Engineering
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About Cadence
Provides electronic design automation software and IP for designing, verifying, and optimizing complex semiconductor chips and systems.