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Lead Design Engineer

Own the analog/AMS design flow for high-speed memory interface PHYs at Cadence
San Jose, California, United States
Senior
$114,800 – 213,200 USD / year
16 hours agoBe an early applicant
Cadence

Cadence

Provides electronic design automation software and IP for designing, verifying, and optimizing complex semiconductor chips and systems.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Lead Design Engineer – Roles & Responsibilities

  • Contribute to analog and AMS design activities for high-speed memory interface PHYs, with strong hands-on execution capability
  • Evaluate architecture models and feasibility studies to assess performance, power, area, and scalability trade-offs
  • Support early architecture exploration by providing circuit-level insight and validating architectural assumptions
  • Actively support silicon bring-up, lab debug, and characterization, including root-cause analysis of analog, AMS, and PHY-level issues
  • Show willingness to jump into any technical domain that requires immediate attention to unblock teams or customers
  • Contribute to technical documentation by identifying gaps, proposing improvements, and supporting the creation of design documents and architecture support material
  • Act as a dependable technical contributor during critical phases such as silicon validation, and customer escalations
  • Apply AI-based approaches to automate repetitive tasks, and enhance engineering productivity

Required Qualifications

  • M.S. degree in Electrical Engineering, Computer Engineering, or related field (required or strongly preferred)
  • Minimum 7 years of industry experience in analog / AMS design, memory PHYs, or high-speed IO
  • Strong hands-on experience with analog and AMS circuits
  • Solid background in DDR / LPDDR memory interfaces

The annual salary range for California is $114,800 to $213,200. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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Lead Design Engineer
San Jose, California, United States
$114,800 – 213,200 USD / year
Engineering
About Cadence
Provides electronic design automation software and IP for designing, verifying, and optimizing complex semiconductor chips and systems.