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Lead Design Engineer

Lead the physical design of complex semiconductor blocks from RTL to GDS in advanced technology nodes
Hyderabad, Telangana, India
Senior
yesterday
Cadence

Cadence

A leading provider of electronic design automation (EDA) software and engineering services for the creation of semiconductors and electronics.

At Cadence, We Hire And Develop Leaders And Innovators Who Want To Make An Impact On The World Of Technology.

Role: Lead Design Engineer, Digital Physical Design

Responsibilities

  • Block level netlist to GDS delivery
  • Subsystem level floorplan, PnR and timing closure
  • FCFP/FCI/FCT activities - Full chip floor planning, Full chip integration, Full chip timing
  • Leading/Guiding a team of 2-3 Engineers

Required Skills

  • 5+ years of experience in PnR and STA
  • Handson experience in RTL/Netlist to GDS delivery of blocks
  • Good understanding of DFT stitching and clock tree strategies
  • Strong at density and congestion issues resolution
  • Complex blocks floorplan, PnR and STA such as DDRIP. PCIE IP
  • Capable of doing PV and IREM fixes along with the timing
  • Exposure to any of 7/6nm, 5/4nm & 3/2nm technologies
  • TCL and PERL scripting knowledge and experience in writing the scripts
  • Good exposure to Cadence EDA tool set needed for PD

Optional Skills

  • Handson experience in low power designs
  • Handson experience on subsystem level activities
  • Flat chip or small hier chip FC activities
  • Complex IP integration like DDR and PCIe
  • Experience in guiding freshers/interns

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Lead Design Engineer
Hyderabad, Telangana, India
Engineering
About Cadence
A leading provider of electronic design automation (EDA) software and engineering services for the creation of semiconductors and electronics.