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Lead Design Engineer
Lead the physical design efforts for high-speed DDR and HBM IP
Shanghai
Junior
yesterday
Cadence
Provides electronic design automation software and IP for designing, verifying, and optimizing complex semiconductor chips and systems.
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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Our team delivers many high-performance products based on the industry's advanced technology with high frequencies up to 6400MHz. Our product processes include TSMC 3nm/5nm/7nm/12nm and Samsung 4nm/5nm/7nm/8nm/10nm, etc. In the team you will face great challenges such as FP, CTS, STA, etc. At the same time, you will get rich experience and advanced methodology.
Job Responsibilities:
- Focus on high speed digital DDR and HBM IP physical implementation, develop necessary scripts or tools to enhance current PD design flow.
- Work in product projects, including but not limited to: complete the project tasks; solve design issue and provide flow to check and avoid similar issue; analyze and summarize PPA optimization methodologies and results, implement optimal design parameters and flows for different projects.
Job Requirement:
- MS in EE with at least 3 years relevant IC design experience
- Good physical design experience in the digital implementation domain including Floorplan, CTS, STA, Physical verification, Power analysis.
- Solid background in circuits, electronics, physics, be willing to learn new technology for cutting edge process node and advanced design methodology.
- Skilled in scripting language, such as Perl, C shell, TCL, Makefile, Python.
- Familiar with EDA tools like Innovus, ICC, Calibre, Tempus, PrimeTime, etc
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About Cadence
Provides electronic design automation software and IP for designing, verifying, and optimizing complex semiconductor chips and systems.