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Design Engineer II
Manage chip level IO planning and RDL routing for advanced semiconductor projects
Hyderabad, Telangana, India
Mid-Level
17 hours agoBe an early applicant
Cadence
A leading provider of electronic design automation (EDA) software and engineering services for the creation of semiconductors and electronics.
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Experience: 3 to 6+ Years
Qualification: BE or B.Tech / ME or M.Tech
Responsibilities:
- Chip Level IO Planning, Bump Planning and RDL Routing
- Coordination with FCFP and Block Owners for the RDL integration
- IP Integration activities for PLL, PVT Sensors etc
Required Skills:
- 3+ years of experience in IO & RDL
- Handson experience in IP DRC and LVS checks and IP Integrations
- Good in debugging the LVS issues related to IO Plan
- Good understanding of Latch up issues, soft checks etc
- Understanding of PnR flow
- Good exposure to Cadence EDA or any other tool set needed for IO & RDL
Optional Skills:
- Complex IP hardening like DDR, PCIe, MiPi etc
- Idea on PG Mesh Structures and Track Optimizations
- TCL and PERL scripting knowledge and experience in writing the scripts
- Hands on experience in low power designs
- Exposure to any of 7/6nm, 5/4nm & 3/2nm technologies
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About Cadence
A leading provider of electronic design automation (EDA) software and engineering services for the creation of semiconductors and electronics.