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Design Engineer II

Design and verify high-speed protocol interfaces for modern ICs
Shanghai
Junior
21 hours agoBe an early applicant
Cadence

Cadence

Provides electronic design automation software and IP for designing, verifying, and optimizing complex semiconductor chips and systems.

At Cadence, We Hire And Develop Leaders And Innovators Who Want To Make An Impact On The World Of Technology

Responsibilities:

  1. Working in Cadence Flagship Emulation and Prototyping product line;
  2. Responsible for designing, developing, modifying and productizing protocol products like PCIe, advanced Ethernet and many more which are crucial to modern IC design and verification.
  3. Perform as individual contributor on protocol projects involving logic RTL design, UVM based verification, board design/debug and documentation etc.
  4. Work on complex problems related to protocol or system integration level issues, electrical or timing closure issues, RTL design or verification methodologies.

Requirements:

  • The position requires MSEE or equivalent, with experience in logic design and debug.
  • Must have excellent communication skills, both written and verbal.
  • RTL design experience using Verilog is required along with experience in using RTL verification tools and flows.
  • Experience in FPGA design for Xilinx products is strongly recommended.
  • UVM verification experience is desired.
  • Experience with scripting languages like Perl, TCL C-shell is desired.

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Design Engineer II
Shanghai
Engineering
About Cadence
Provides electronic design automation software and IP for designing, verifying, and optimizing complex semiconductor chips and systems.