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Design Engineer I

Design and verify DSP algorithms for high-speed SerDes in Cadence products
San Jose, California, United States
Entry Level
$88,900 – 165,100 USD / year
16 hours agoBe an early applicant
Cadence

Cadence

Provides electronic design automation software and IP for designing, verifying, and optimizing complex semiconductor chips and systems.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

DSP algorithm design for high-speed serdes. Modeling of end-to-end system including analog and digital hardware. Simulation and reporting of anticipated performance of HSS designs under development. Verification of models with lab measurements and experiments.

The annual salary range for California is $88,900 to $165,100. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We're doing work that matters. Help us solve what others can't.

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Design Engineer I
San Jose, California, United States
$88,900 – 165,100 USD / year
Engineering
About Cadence
Provides electronic design automation software and IP for designing, verifying, and optimizing complex semiconductor chips and systems.