✨ About The Role
- The Package Design Engineer will be responsible for the overall design of ASIC package designs, focusing on signal integrity, power integrity, manufacturability, reliability, and thermal aspects.
- The role involves collaborating with a global R&D team to develop high-performance package designs for ASICs used in AI, networking, HPC, and 5G base stations.
- The engineer will contribute to the design of critical structures for SerDes, ADC/DAC, and DDR, ensuring high-speed performance.
- The position requires effective communication and cooperation with internal team members and external vendor designers across multiple time zones.
- The engineer will also be tasked with identifying and implementing efficiency improvements within the design process.
âš¡ Requirements
- The ideal candidate will have a strong background in flip-chip BGA package design, particularly with high-speed SerDes.
- A minimum of 8 years of experience in the relevant field is required, showcasing a deep understanding of package-level signal integrity and power integrity.
- Proficiency in Cadence SKILL for Allegro or similar design-automation coding is essential, with a preference for candidates with 3 or more years of experience.
- Strong project management skills are necessary, as the role involves scheduling, prioritizing, and tracking work across multiple projects.
- The candidate should possess excellent self-management and organizational skills to thrive in a collaborative, worldwide team environment.