✨ About The Role
- The role involves architecting and designing memory subsystems for large memory blocks.
- Responsibilities include implementing RTL of subsystem designs and performing place and route tasks.
- The job requires ensuring design closure through timing, DRC, LVS, EM/IR, and other checks.
- The candidate will be involved in gate netlist synthesis and debugging logical equivalency checkers.
- Familiarity with memory behavior and proficiency in writing automation scripts is expected.
âš¡ Requirements
- The ideal candidate will have a minimum of 8 years of relevant experience in memory subsystem design.
- A Bachelor's degree in Electrical Engineering is required for this position.
- Strong design skills and the ability to write and debug Verilog RTL code are essential.
- The candidate should be proficient in place and route expertise and running design closure tools.
- Good communication, interpersonal, and leadership skills are necessary for collaboration within the team.
- The successful individual will be motivated, self-driven, and capable of multitasking effectively.