✨ About The Role
- The role involves implementing and verifying DFT methodologies specifically for HBM, DDR, and SerDes designs.
- The engineer will collaborate with design and architecture teams to identify and define critical testability requirements.
- Responsibilities include generating, verifying, and debugging test vectors before tape release and during the silicon bring-up phase.
- The position requires interfacing with customers and various engineering teams located globally.
- The engineer will also assist with silicon failure analysis, diagnostics, and yield improvement efforts.
âš¡ Requirements
- The ideal candidate will have a strong background in Design for Test (DFT) methodologies, particularly in HBM, DDR, and SerDes designs.
- A proven track record in DFT verification and experience with advanced simulation tools is essential for success in this role.
- The candidate should possess excellent analytical skills to analyze DFT-related data and provide insights for continuous design improvements.
- Strong collaboration skills are necessary to work effectively with cross-functional teams, including design and architecture teams.
- Staying updated with the latest trends and technologies in DFT, HBM, and SerDes is crucial for driving innovation within the team.