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Design Verification Engineer
Identify and apply formal verification techniques to complex design interfaces.
Remote
Expert
$107,000 - 171,000 USD / year
4 months ago
✨ About The Role
- The Design Verification Engineer will be responsible for formal and functional verification of complex designs.
- The role involves identifying designs suitable for formal verification and applying formal verification techniques.
- Responsibilities include test planning, test bench development, test execution, and achieving functional/code coverage closure.
- The position requires expertise in System Verilog, particularly in writing System Verilog Assertions (SVAs) for formal verification.
- The engineer will work closely with interface IP designs and may engage with high bandwidth memory and Ethernet/PCIE/CXL designs.
âš¡ Requirements
- The ideal candidate will have over 10 years of experience in design verification, particularly with complex designs and external interfacing IPs.
- A strong understanding of System Verilog assertions and the ability to write effective coverage and assertion properties is essential.
- Experience in architecting reusable and constrained random test benches from scratch is crucial for success in this role.
- The candidate should have expertise in verification methodologies like UVM and be familiar with high bandwidth memory (HBM) PHY/controller subsystems.
- Strong communication skills are necessary for external customer support related to design IPs or VIPs.
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