✨ About The Role
- The role involves working on design implementation activities related to place and route, timing closure, and physical verification.
- Candidates will be expected to drive tools and methodologies to achieve desired PPA metrics.
- Responsibilities include performing equivalence checks, static timing analysis, and power optimization.
- The position requires hands-on experience with timing analysis and place and route tools for ASIC/SoC design.
- Experience with full chip tapeout based on 7nm and lower technologies is highly preferred.
âš¡ Requirements
- The ideal candidate will have a strong background in electrical or computer engineering, with a minimum of 8 years of relevant experience.
- Proficiency in design implementation activities at both block and SoC levels is essential for success in this role.
- The candidate should be a self-starter, capable of working independently while also being an effective team player in a global environment.
- Excellent problem-solving skills and the ability to adapt to new tools and methodologies quickly are crucial.
- Strong communication skills are necessary to collaborate effectively with team members and stakeholders.