View All Jobs 1902

Sr Staff/Principal FPGA Design Engineer

Create solutions on the FPGA platform to support Array Lab’s radar and communications payload.
Palo Alto, California, United States
2 months ago
Array Labs

Array Labs

We're building satellites to create a real-time 3D map of the world.

✨ About The Role

Sr Staff/Principal FPGA Design Engineer

Palo Alto, California
Engineering /
Full-Time
/ On-site
Array Labs is building a distributed radar imaging constellation to power the first accurate, real-time 3D model of the world.

The Hardware Engineering team at Array Labs is responsible for the analysis and design of our satellite and ground-station hardware platforms. These platforms tend to be a heterogeneous mix of various subsystems like compute, memory, peripherals with high-speed interfaces, RF, sensing, power management, navigation, and controls. The focus areas of the Hardware Engineering Team can be split into Aerospace/Avionics, Electrical/Electronics (EE) and Communications/Radar engineering. As an FPGA Design Engineer in the Hardware Engineering team, you will create solutions on our FPGA platform to support Array Lab’s radar and communications payload as well as our ground infrastructure. You will work with Communication Systems and Radar Algorithms teams to define, implement, and test various algorithms, control systems, and modem systems on our FPGA platform. The role requires implementing proprietary algorithms and integrating third-party IPs on the FPGA platform. This is a unique opportunity to join our early team and make a significant impact by contributing to the creation of a brand-new platform free from any legacy limitations.


Responsibilities:

    • Collaborate with Radar, Communications, and RF engineers to define, implement, and test various signal processing algorithms and digital logic functions in FPGAs
    • Work with HW Design Engineers and Embedded SW engineers to rapidly prototype and bring up satellite payloads that combine FPGA, processors, firmware, sensors, and networking functionality
    • Take full responsibility for executing RTL design with or without HLS (High-Level Synthesis), physical implementation, timing closure, and validation through simulation
    • Create robust software infrastructure using modern coding techniques to ensure that FPGA images seamlessly integrate into our hardware platform's Board Support Package while also functioning independently


Basic Qualifications:

    • B.S in Electrical or Computer Engineering
    • 11+ years of experience in modern FPGA design, implementation, and verification
    • Solid understanding of FPGA logic Synthesis, partitioning, routing and timing closure
    • Excellent teamwork and communication skills
    • Learns new concepts rapidly, completely, and in a self-directed manner
    • High levels of self-motivation and personal accountability
    • Ability to work in a fast-paced environment under significant time constraints
    • Experience in FPGA or ASIC design in VHDL, Verilog, or SystemVerilog
    • Experience with FPGA tools, preferably Xilinx Vivado


Preferred Skills and Experience:

    • Master's degree in Electrical or Computer Engineering
    • 6+ years of FPGA prototyping experience (compilation, debugging and throughput tuning) on Xilinx/Altera/Lattice Semiconductor FGPAs
    • Strong logic design, RTL coding (Verilog / VHDL), and debugging skills
    • Familiar with design constraints, logic synthesis, timing closure analysis, and clock/reset domain crossing checks
    • Proficiency with FPGA synthesis and implementation tools (e.g. Xilinx Vivado, Altera Quartus II),  HDL simulators (VCS, Questa, IES), HDL Lint tools (e.g. Spyglass), and Power Analysis tools.
    • Experience implementing fixed-point DSP blocks in RTL, such as IIR and FIR filters, modulator/demodulator, encoder/decoders PLLs, CORDIC operations and FFT processors, and CORDIC processors
    • Familiarity with custom IP verification and integration
    • Experience creating UVM-based test benches for verification of FPGA designs
    • Familiarity with processor architecture and associated communications protocols such as AXI, DMA, I2C, UART, SPI, PCIE, USB, and Ethernet.
    • Proficiency in scripting languages such as Python and Bash
    • Experience with high-speed SERDES interfaces, Ethernet, and IP networking


ITAR Requirements:

    • To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State.


Equal Opportunity Employer

    • Array Labs is an Equal Opportunity Employer. Employment decisions are made on the basis of merit, competence, and job qualifications and will not be influenced in any manner by gender, color, race, ethnicity, national origin, sexual orientation, religion, age, gender identity, veteran status, disability status, marital status, mental or physical disability or any other legally protected status.


Interview Process
We will conduct three interviews via Zoom; the typical process takes around 2-4 weeks to complete from start to finish.

Hiring and Compensation Strategy
Our hiring and compensation strategy is simple:

1) find uncommonly good people
2) pay them uncommonly well

You can anticipate competitive pay, with high flexibility between salary and equity-based compensation.

Why you should join Array Labs
Array Labs is launching a constellation of satellites to create the first high-resolution, real-time, three-dimensional model of Earth. Our next-generation satellite technology will offer image quality 60x greater than traditional techniques, profoundly expanding humanity’s ability to understand and respond to events on a global scale.

In forging an affordable, accessible, accurate representation of Earth, our work has the potential to transform the face of dozens of fields, including autonomy, telecommunications, disaster relief, gaming, climate science, defense and construction.

+ Show Original Job Post
























Sr Staff/Principal FPGA Design Engineer
Palo Alto, California, United States
Engineering
About Array Labs
We're building satellites to create a real-time 3D map of the world.