Principal Engineer - Silicon Packaging Architect

Silicon Packaging Architect

Intel's Central Engineering Group is seeking a Silicon Packaging Architect, responsible for bridging silicon design and advanced packaging to deliver high-performance, cost-effective solutions for next-generation SOCs and DDR PHY interfaces.

Key responsibilities include: leading the co-design of silicon and package, focusing on DDR PHY and mixed signal IP integration for server SOCs; designing bump maps, floor plans, and managing area constraints for PHYs, collaborating closely with packaging technical experts; conducting hands-on package extractions and simulations (signal integrity, power integrity) to assess package trace and electrical impacts, and performing risk assessments for bump-out strategies; finalizing bump-out, floor plan, and area decisions at the end of tech readiness phases; interfacing with packaging teams on advanced technologies (e.g., C4 bumps, micro bumps, EMIB, hybrid bonding as needed); focusing on design, development, and architecture, not process or materials engineering.

Required experience includes: experience in both silicon design (preferably mixed signal/analog) and packaging co-design; background in DDR, SOC, or similar high-speed interface development; hands-on expertise with bump mapping, floor planning, and packaging constraints; proven ability to collaborate across silicon and packaging teams, including risk assessment and simulation; familiarity with advanced packaging technologies (hybrid bonding, EMIB, etc.) is a plus but not required; individual contributor or principal engineer level preferred; management experience is not required; experience at leading companies in advanced packaging and PHY design (e.g., Apple, Broadcom, Qualcomm, Micron, AMD, Nvidia).

Qualifications include: bachelors in electrical engineering, chemical engineering, mechanical engineering, material science or similar field (Master's or Ph.D. preferred); 10+ years in silicon and packaging co-design.