This position involves the definition, design, verification, and documentation of ASIC and/or FPGA developments. The role requires in-depth experience using RTL simulation tools and knowledge of System Verilog object-oriented programming and the Universal Verification Methodology (UVM). Responsibilities include determining architecture, system simulation and detailed design approach, defining module interfaces, creating test and simulation plans, and verifying test results. The candidate must have proficiency in ASIC/FPGA engineering concepts, principles, and theories, and be able to communicate effectively with senior levels of internal work groups and external customers. The position also demands a commitment to ongoing professional development.