Collateral Device Engineer

Device Technologist

Manufacturing Development and Customer Engineering (MDCE) organization serves as the bridge between advanced technology development and practical, scalable manufacturing, ensuring that innovative solutions can be successfully produced and delivered to foundry customers. MDCE Device org is seeking a highly skilled and experienced device technologist with expertise in device collateral development and design rule implementation for foundry technology development.

As a device technologist, you will be responsible for developing device collateral including test chip designs, DTCO, product scribe line layouts, manage OPC/Mask requests and managing design rules and waivers for technologies currently in large volume manufacturing. The role focuses on general-purpose logic CMOS technologies to support a broad spectrum of products and markets including high performance compute, mobile, mixed signal, memory controllers, and other diverse applications.

Key Responsibilities:

• Design and develop comprehensive device collateral including test chip architectures and product scribe line layouts to support technology characterization and monitoring
• Collaborate with Technology Development teams to establish and refine design rules for newly developed device architectures and customize collateral to meet customer-specific requirements
• Develop and manage design-rule waiver processes, ensuring proper documentation and risk assessment for customer applications
• Create and optimize scribe line monitoring structures for yield enhancement and process control in high-volume manufacturing
• Work with manufacturing teams to implement device collateral that meets specifications, yield targets, and provides robust process monitoring capabilities
• Drive the development of standardized test chip methodologies and scribe line layouts that are compatible with Intel's existing manufacturing processes and platforms
• Analyze device parametric data from test chips and scribe line structures to drive continuous improvement in device performance and manufacturability
• Provide technical guidance on design rule compliance and waiver justifications to cross-functional teams and customers
• Stay updated with industry trends in device collateral design, test methodologies, and design rule evolution to inform development strategies.

Ideal candidate must demonstrate:

• Excellent technical problem-solving skills with ability to balance design rule compliance with customer flexibility needs
• Ability to work collaboratively in globally diverse, cross-disciplinary teams to develop innovative device collateral solutions
• Proven track record of delivering device collateral solutions in a fast-paced manufacturing environment
• Desire to learn, lead, and influence cross-functional teams in collateral development and design rule optimization

Qualifications:

Minimum Qualifications:

• Master's degree in Electrical Engineering, Physics, or related field with 7+ years of experience in CMOS device engineering with focus on test chip design and device collateral development.
• Demonstrated expertise in CMOS semiconductor device physics and test chip design for advanced transistor device architecture.
• Experience in scribe line layout design and process monitoring structure development.
• Proficiency in design rule development, validation, and waiver management processes.
• Strong understanding of DTCO skills including understanding of SRAM, Standard cells and be the key interface and bridge between Process Integration, Yield, Device and Design.

Preferred Qualifications:

• Ph.D. degree in Electrical Engineering, Physics, or related field with 5+ years of experience in CMOS device engineering and collateral development
• Demonstrated experience with design of experiment (DOE) principles applied to device collateral optimization
• Strong skills in data analysis, scripting, and statistical techniques for test chip data interpretation.
• Hands-on experience in advanced node test chip design and scribe line optimization for 3nm-16nm FinFETs and sub 3nm GAA FETs
• Experience with design rule checker (DRC) development and physical verification flows
• Experience in High-Volume Manufacturing environment with focus on yield monitoring and process control structures
• Knowledge of statistical process control (SPC) and advanced data analytics for device collateral optimization
• Knowledge of mask generation including Boolean/OPC

Job Type: Experienced Hire

Shift: Shift 1 (United States of America)

Primary Location: US, California, Santa Clara

Additional Locations: US, Arizona, Phoenix, US, Oregon, Hillsboro

Business group: Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.

Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits: We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Annual Salary Range for jobs which could be performed in the US: $190,650.00-269,150.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role: This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. Job posting details (such as work model, location or time type) are subject to change.