Senior Optical Signal Integrity / Power Integrity (si/pi) Engineer

Senior Optical Signal Integrity / Power Integrity (SI/PI) Engineer

Arista Networks is an industry leader in data-driven, client-to-cloud networking for large data center, campus and routing environments. What sets us apart is our relentless pursuit of innovation. We leverage the latest advancements in cloud computing, artificial intelligence, and software-defined networking to provide our clients with a competitive edge in an increasingly interconnected world. Our solutions are designed to not only meet the current demands of the digital landscape but to also anticipate and adapt to future challenges.

At Arista we value the diversity of thought and perspectives that each employee brings to the table. We believe that fostering an inclusive environment, where individuals from various backgrounds and experiences feel welcome, is essential for driving creativity and innovation.

Our commitment to excellence has earned us several prestigious awards, such as Best Engineering Team, Best Company for Diversity, Compensation, and Work-Life Balance. At Arista, we take pride in our track record of success and strive to maintain the highest standards of quality and performance in everything we do.

Job Description

Arista Networks is seeking a Senior Optical Signal Integrity / Power Integrity (SI/PI) Engineer to lead the design, simulation, and validation of high-speed electrical interconnects and power delivery networks (PDNs) for next-generation optical modules and engines — including 1.6T, and emerging high density platforms using 224G, and 448G signaling. This position is critical in ensuring system-level performance across advanced photonic systems through robust SI/PI design and validation. You'll work closely with hardware architects, ASIC vendors, layout, packaging, and optical teams to co-optimize performance, manufacturability, and reliability for state-of-the-art networking hardware.

• Lead signal integrity (SI) and power integrity (PI) efforts for high-speed optical transceiver modules, high density optical interconnect platforms.
• Design and simulate high-speed channels up to 448G per lane (e.g., 224G/448G PAM4) across PCBs, packages, and connectors.
• Perform pre- and post-layout SI/PI simulations using tools like Ansys HFSS, Keysight ADS, Cadence Sigrity, and SiSoft QSI.
• Develop and validate PCB stackups, via structures, high-speed breakout regions, and connector transitions to meet compliance with IEEE, CEI, and MSA standards.
• Work closely with electrical, optical, and layout teams to define routing constraints, reference plane designs, and return path continuity for minimal signal degradation.
• Design and optimize PDNs to meet target impedance, minimize noise coupling, and support fast transient loads for high-speed DSPs and ICs.
• Provide SI/PI layout guidelines to PCB designers and review placement/routing for high-speed paths and power domains.
• Collaborate with validation teams to perform measurements (TDR, VNA, eye diagram, jitter, BER) and correlate with simulation models.
• Engage with ASIC, connector, and packaging vendors to support co-design and channel optimization across multiple integration layers.
• Drive root cause analysis of SI/PI-related issues during validation and production builds.

Qualifications

• B.S. or higher in Electrical Engineering, Applied Physics, or a related discipline.
• 7+ years of experience in SI/PI engineering for high-speed interconnects in optical or networking hardware.
• Proven experience with 112G, 224G, and 448G PAM4 signaling and related SI/PI challenges.
• Strong understanding of PCB stackup design, via modeling, impedance control, and crosstalk mitigation.
• Expertise in signal integrity simulation tools such as Ansys HFSS, Keysight ADS, Sigrity, or similar.
• Experience with power delivery design, including decoupling strategies, PDN impedance analysis, and noise mitigation techniques.
• Familiarity with transceiver MSA form factors (QSFP-DD, OSFP) and standards from IEEE, CEI, OIF.
• Hands-on experience using TDRs, VNAs, oscilloscopes, and other lab equipment to validate simulation results.
• Excellent problem-solving, documentation, and cross-functional communication skills.

Preferred Qualifications

• M.S. or Ph.D. in Electrical Engineering or a related field with emphasis on high-speed or mixed-signal systems.
• Experience with co-packaged optics, chiplet-based architectures, or advanced substrate technologies.
• Familiarity with EMI/EMC considerations and signal/power isolation in densely integrated photonic-electronic systems.
• Understanding of thermal and mechanical effects on SI/PI performance and long-term reliability.
• Experience working with fabrication vendors, ASIC teams, and contract manufacturers to ensure end-to-end channel integrity.

Compensation Information:

The new hire base pay for this role has a pay range of $150,000 to $230,000. Arista offers different pay ranges based on work location, so that we can offer consistent and competitive pay appropriate to the market. The actual base pay offered will be based on a wide range of factors, including skills, qualifications, relevant experience, and work location. The pay range provided reflects base pay only and in addition certain roles may also be eligible for discretionary Arista bonuses and equity. Employees in Sales roles are eligible to participate in Arista's Sales Incentive Plan, which pays commissions calculated as a percentage of eligible sales. US-based employees are also entitled to benefits including medical, dental, vision, wellbeing, tax savings and income protection. The recruiting team can share more details during the hiring process specific to the role and location.

Arista Networks is an equal opportunity employer. Arista makes all hiring and employment-related decisions in a non-discriminatory manner without regard to race, color, religion, sex, sexual orientation, gender identity, national origin or any other factor determined to be unlawful under applicable federal, state, or law law. All your information will be kept confidential according to EEO guidelines.