Soc Packaging Engineer

SoC Packaging Engineer

Taipei, Taipei, Taiwan, Hardware

At Apple, we believe our products begin with our people. By hiring a team with varied strengths, we drive creative thought. By giving that team everything they need, we drive innovation. By hiring incredible engineers, we drive precision. And through our collaborative process, we build memorable experiences for our customers. You will become part of a hands-on development team that sets the standard in cultivating excellence, creativity and innovation. Will you help us design the next generation of revolutionary Apple products?

Description

We are looking for a senior level SoC packaging engineer to develop exciting new products. Your role is to interface between internal product/device design, quality, supply chain, and the external suppliers to develop and deploy new packaging technologies. We are looking for individuals who are very innovative with a proven track record to bring packaging solution from concept to high-volume manufacturing.

Responsibilities

Explore and evaluate packaging technologies as our own packaging tool box. Define new package characteristics and specification based on unique module and system level performance, cost, and footprint. Work with leading foundry & assembly suppliers on advanced organic and silicon interposer interconnect package development from design, new material, new equipment selection and establish robust process/process flow. Perform initial proof of concept sample build, process of record, package and process qualification, reliability test, yield analysis and continuous improvement. Interface and coordinate with other packaging team members to comply with product development/ramp schedule. Deliver package/packaging milestones on time. Define packaging roadmap based on long term packaged product requirements. Work closely and manage suppliers' R&D activities. At least 5~10% travel to domestic and international locations.

Minimum Qualifications

M.S or Ph.D. degree in mechanical engineering, physics, materials science or similar disciplines with a minimum of 5 years of experience in IC packaging. In-depth knowledge in large body size MCM package technologies inclusive of SoC & HBM integration, RDL & Silicon with deep trench capacitor interposer and Chip-on-Wafer processes.

Preferred Qualifications

Good understanding to organic package process & material characterization such as micro bump plating, RDL lithography, molding compound and under-fill. Knowledge in HBM integration and reliability characterization, advanced silicon node BEOL and device physics or component/board level reliability testing are plus. Proven track record to drive issue resolution with good understanding to root cause and physics, motivate and mobilize all levels within supplier to accomplish any given task. Able to perform independent research and development work with minimal supervision. Good written and verbal communication skills. Able to present ideas, design concepts, data and plan with high confidence at internal or external meetings.