PMU Design Verification Engineer (m/f/d)

PMU Design Verification Engineer

At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game?! We have an opportunity for a driven and highly committed Design Verification Engineer. As a member of our multifaceted group, you will have the unique opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every day! We are looking for a Design Verification Engineer in our team, who will enable bug-free first silicon for our mixed-signal designs, in close collaboration with Digital and Analog Design engineers. The responsibilities include all phases of pre-silicon verification including, establishing design verification methodology and test-plan development. Additional responsibilities will include verification environment development, such as stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.

Description

In this role you will:

• Develop verification plans in coordination with design leads and architects.
• Be responsible for planning, building and maintaining verification test bench components and environments.
• Generate directed and constrained random tests. Run simulations and debug design and environment issues.
• Create functional coverage points, analyze coverage, and improve test environment to target coverage holes.
• Craft automated verification flows for block and chip level verification.
• Apply knowledge of hardware description languages (VHDL/Verilog), hardware verification languages (SystemVerilog/UVM), and logic simulators to verify complex designs.
• Work with other block and core level engineers to ensure a perfect verification flow.

Minimum Qualifications

• Master’s degree in Electrical Engineering, Embedded Systems, Computer Science or related field
• Excellent communication and interpersonal skills combined with the ability to collaborate
• Fluency in English
• Deep knowledge of SystemVerilog and UVM
• Experience developing scalable and portable test-benches
• Experience with constrained random verification environments
• Experience defining coverage space, writing coverage model, analyzing results
• Experience with Assertion Based Verification

Preferred Qualifications

• Experience in Formal Verification (Formal Linting, Formal Connectivity, User Property Verification) is a plus
• Experience with Python, Perl or TCL
• Understanding of AI and ML and their potential application to verification
• Apple is an equal opportunity employer that is committed to inclusion and diversity
• We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or other legally protected characteristics
• Apple is committed to working with and providing reasonable accommodation to applicants with physical and mental disabilities