Performance Model Integration Engineer, Platform Architecture

Performance Model Integration Engineer, Platform Architecture

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products very quickly. Bring passion and dedication to your job and there's no telling what we can accomplish together. Do you love crafting elegant solutions to highly complex challenges? Can you intrinsically see the importance of every detail? At Apple, our Platform Architecture group is responsible for connecting our hardware and software into one unified system. Join this team, and you'll collaborate with engineers across Apple to build and deploy forward-looking prototype systems that contribute to the development of our world renowned hardware and software architecture. This multi-disciplinary role ties together analysis from low level software tuning for custom CPU pipelines through SOC level cache and memory subsystem performance. You and your team will develop tools that are used to ensure that every product we make performs exactly as intended. Together, our work will be the reason millions of customers feel that they can trust our devices every single day.

Description

Apple's Platform Architecture group is seeking a performance model integration engineer, who will develop novel technologies for accelerating the development and verification of silicon. You will work with our world leading silicon engineering teams and firmware development teams on next generation chips, which end up in the hands of millions of users worldwide.

Responsibilities

Develop and maintain RTL-based systems performance models, integration CPU IP and peripheral components. Validate, own, and ship models to cross-functional internal customers. Support and clearly communicate with engineers from multiple disciplines (software, architecture, verification, and validation). Debug functionality and performance of large IP-based systems using simulation. Work independently and manage deliverables to different teams. Occasional travel to development groups in the US.

Minimum Qualifications

B.S. degree in Computer Science, Electrical Engineering, or similar. Experience programming in Verilog/SystemVerilog. Experience programming in C/C++. Background in Computer Architecture. Experience debugging software and hardware.

Preferred Qualifications

10+ years of relevant experience. Experience with SystemVerilog DPI (C/C++). Experience developing HDL based testbenches for Emulation / Acceleration. Experience developing bus functional models, and using Verification IP. Familiarity with CPU, IP, SoC performance analysis, latency characterization. Skilled in debugging C/C++ including X86/ARM Assembly. Scripting ability in Python or Lua. Strong written and verbal communication skills.