Hardware Design Engineer 4

Engineer With Deep Expertise In RTL-to-GDSII Flows

Candidate Location Requirements: Silicon Valley, CA – Onsite 3 Days a Week

Pay Rate: $79.00 - $82.00 / hour

Role Overview

We are seeking a highly skilled and motivated engineer with deep expertise in RTL-to-GDSII flows, specifically using Synopsys Fusion Compiler and RTL Architect (RTLA). This role is pivotal in driving synthesis quality, power-performance-area (PPA) optimization, and methodology development for advanced node SoC designs.

Key Responsibilities

Own and optimize RTL-to-GDSII implementation flows using Synopsys Fusion Compiler, including synthesis, placement, routing, and signoff.

Develop and maintain RTLA-based power estimation and optimization flows, integrating with PrimePower RTL and design environments.

Collaborate with RTL and physical design teams to define timing constraints, UPF-based power intent, and switching activity annotations for accurate power analysis.

Drive methodology improvements for early RTL power estimation, scenario-based analysis, and dynamic power optimization.

Support debug and convergence of synthesis flows including constraint validation, floorplan integration, and flow automation.

Interface with EDA vendors (Synopsys preferred) to evaluate tool enhancements, report issues, and guide roadmap alignment.

Provide training and documentation to internal teams on best practices for synthesis and power-aware design.

Required Qualifications

7+ years of experience in RTL synthesis and physical implementation using Synopsys tools (Fusion Compiler, Design Compiler, PrimeTime).

Strong command of RTLA and PrimePower RTL flows, including switching activity modeling and scenario-based analysis.

Proficiency in scripting (TCL, Python) for flow automation and debugging.

Deep understanding of timing constraints, UPF, and low-power design methodologies.

Experience with Linux and bash scripting skills are preferred.

Familiarity with advanced process nodes and associated challenges in timing, congestion, and power closure.

Preferred Qualifications

Experience collaborating with EDA vendors on tool evaluation and runtime profiling.

Exposure to dashboarding and reporting automation for synthesis metrics.

Prior contributions to flow migration or tool benchmarking initiatives.

EEO Employer

Apex Systems is an equal opportunity employer. We do not discriminate or allow discrimination on the basis of race, color, religion, creed, sex (including pregnancy, childbirth, breastfeeding, or related medical conditions), age, sexual orientation, gender identity, national origin, ancestry, citizenship, genetic information, registered domestic partner status, marital status, disability, status as a crime victim, protected veteran status, political affiliation, union membership, or any other characteristic protected by law. Apex will consider qualified applicants with criminal histories in a manner consistent with the requirements of applicable law.