Staff Engineer, Design Verification

Staff Engineer For Ic Verification

Analog Devices, Inc. is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™.

The PES Milan team is seeking a motivated Staff Engineer for IC Verification to provide support to our Personal Electronics Solutions located in Milan, Italy.

Minimum Degree required: MS degree in Electronics and Communications Engineering or closely related field of study

Job Description Summary: We know that you have a lot to offer, and you're ready to take on any challenge. At Analog Devices, you'll be given opportunities to learn, grow and have fun. You can expect to work on meaningful and interesting projects and to join a team of dynamic, skillful and experienced professionals. The Consumer Group is seeking a Mixed-Signal Verification (MSV) Engineer to verify top-level mixed-signal architecture and design, and to support the growth of its Ultra Low Power (ULP), space-Saving Power and Battery Management Solutions business. The position is in ADI Milan (Italy) design center.

Job Description: Responsibilities may include, but are not limited to:

• Read and understand Digital designs in RTL (Verilog)
• Read and understand transistor level designs of circuits (Schematics)
• Work with the design team to understand the design intent and bring up the verification plan and schedule
• Develop Real-Number models (Verilog-AMS/SV-AMS) to reproduce analog circuits behavior
• Create test benches and tests for specific mixed-signal products
• Improve verification flow for broad use across products and quick reuse on new products
• Complete verification of complex projects on schedule and coordinate the verification activity
• Cooperate with cross-functional teams and coordinate priorities to achieve higher productivity
• Follow-up with project team members, to ensure customer satisfaction and gather feedback during and after projects are complete

Minimum Qualifications: Master of Science degree in Electronics and Communications Engineering or closely related field of study plus 6 years of experience in the job offered or closely related occupation. Foreign equivalents accepted. The employer will accept any suitable combination of education, experience or training.

Experience: Deep Knowledge of SystemVerilog (IEEE 1800), Experienced with UVM (Universal Verification Methodology) (IEEE 1800.2-2020), Scripting and design automation (TCL, PERL, RUBY, SHELL), Implementing mixed signal digital design verification methodologies and flows, Modeling of analog (Real Number Models) in Verilog-AMS and SystemVerilog, Experience with Cadence based Verification tools: Virtuoso, Simvision, Xcelium, vManager, Verification Planning and developing verification plan, Architecting and building test benches and environments, Intuitive and analytical understanding of transistor-level circuit design, Knowledge of PSL / SVA Assertions is a plus, Formal Verification is a plus, Previous experience with I2C, PMIC or USB-C is a plus, Fluent in English