Senior Engineer, Yield Enhancement And Defect Reduction

Analog Devices Front-End Fab Quality Engineer

Analog Devices, Inc. is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™.

The ADI Front-End Fab Quality organization is committed to driving customer satisfaction through continuous improvement in front-end manufacturing. This is achieved by applying a systematic approach to quality management, focusing on defect reduction and prevention. The role involves active collaboration across departments, leading cross-functional initiatives aimed at solving complex problems, reducing defects, and enhancing yield. This position is based at ADI's wafer fabrication facility in Camas, Washington.

Responsibilities:

• Defect Process Ownership: Own and manage defect control across multiple semiconductor manufacturing process flows. Continuously monitor SPC trends, perform correlation and commonality analyses to identify root causes, and implement timely corrective actions to prevent inline process excursions. Lead investigations, containment, and disposition of defect excursions and discrepant materials.
• Defect Reduction Strategy: Establish clear goals for reducing yield-limiting defect types. Drive defect reduction initiatives based on Pareto analysis and kill ratios. Develop and implement Out-of-Control Action Plans (OCAPs).
• Defect Metrology Tool Ownership: Provide engineering ownership for defect inspection and SEM review tools. Ensure tool matching and consistency across metrology platforms, establish tool monitoring protocols, and develop robust inspection recipes on automated darkfield and brightfield optical inspection tools and SEM.
• Cross-Functional Leadership: Lead cross-functional teams to address and reduce defectivity. Collaborate closely with Integration, Process, Equipment, and Operations teams on joint defect reduction projects. Design and execute process experiments, perform segmentation analysis, summarize defect data, and propose actionable solutions for process optimization.
• Mentorship and Best Practices: Mentor engineers and technicians, fostering technical growth and knowledge sharing. Benchmark best-known methods (BKMs) and integrate them into fab operations. Manage QA technicians to support engineering tasks and drive project execution.
• DEFECT Data analysis using KLARITY ACE Defect or similar SW

Education and Experience Requirements:

• B.S or M.S in Electronics Engineering, Electrical Engineering, Chemical Engineering or a closely related technical field such as Material Science or Device Physics.
• 4+ years of experience in driving defect reduction & yield enhancement in CMOS/BICMOS, Bipolar device technologies and semiconductor unit processes.
• Excellent communication skills (written, verbal and presentation).
• Excellent data analysis, analytical problem solving, and decision-making.
• Ability to drive projects to completion, meet deadlines, schedules, and commitments.
• Strong organizational skills to manage multiple tasks and able to react to shifting priorities.
• Statistical analysis skills (t test, ANOVA, etc.) required, JMP or other statistical SW.
• Experience with Defect inspection and review tools (KLA/ONTO bright field, KLA dark field, AMAT SEM review, etc.).
• Analyzing Defect to Sort Correlation, Yield Kill Ratios, Spatial Signatures using systems like KLARITY ACE, KLARITY Defect or PDF DataPower, etc.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

EEO is the Law: Notice of Applicant Rights Under the Law.

The expected wage range for a new hire into this position is $94,000 to $129,250. Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors. This position qualifies for a discretionary performance-based bonus which is based on personal and company factors. This position includes medical, vision, and dental coverage, 401k, paid vacation, holidays, and sick time, and other benefits.